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Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
FEATURES
* Four independent adders/subtractors * Two's complement arithmetic * Synchronous operation * Common Clear and Clock * 74F385 is designed for use with serial multipliers in implementing
digital filters and butterfly networks in fast Fourier transforms
PIN CONFIGURATION
CP 1 F0 2 S0 3 B0 4 A0 5 A1 6 20 V CC 19 F3 18 S3 17 B3 16 A3 15 A2 14 B2 13 S2 12 F2 11 MR
DESCRIPTION
The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. The Select (S) input should be Low for the Add (A plus B) mode and High for the Subtract (A minus B) mode. A Low signal on the asynchronous Master Reset (MR) input clears the sum flip-flop and resets the Carry flip-flop to zero in the Add mode or presets it to one in the Subtract mode.
B1 7 S1 8
F1 9 GND 10
SF00928
TYPE 74F385
TYPICAL fMAX 140 MHz
TYPICAL SUPPLY CURRENT (TOTAL) 55mA
ORDERING INFORMATION
DESCRIPTION 20-pin plastic DIP 20-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F385N N74F385D
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS A0 - A3 B0 - B3 S0 - S3 CP MR A operand inputs B operand inputs Function select inputs Clock pulse input (active rising edge) Asynchronous Master Reset input (active Low) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA
F0-F3 Sum or difference outputs NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
1989 Sep 20
1
853-0868 97678
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
LOGIC SYMBOL
5 4 6 7 15 14 16 17
IEC/IEEE SYMBOL
11 1 Z1 C2 S /P-Q
A0 B0 A1 B1 A2 B2 A3 B3 1 11 3 8 13 18 CP MR S0 S1 S2 S3 F0 F1 F2 F3
3 5 4
M3 P Q
2D R 2D 3R 3S
2
3CO/ 3BO
Z4
4(3CI/ 3BI) 8 6 7 13 2 9 12 19 15 14
9
11
VCC = Pin 20 GND = Pin 10
SF00929
18 16 17 19
SF00930
FUNCTION TABLE
INPUTS MR L L H H H H H H H H H H H H H H H H H L X = = = = S L H L L L L L L L L H H H H H H H H A X X L L L L H H H H L L L L H H H H B X X L L H H L L H H L L H H L L H H CARRY FLIP-FLOP STATE Before L H L H L H L H L H L H L H L H L H After L H L L L H L H H H L H L L H H L H OUTPUTS F L L L H H L H L L H H L L H L H H L Subtract Add OPERATING MODE Clear
High voltage level Low voltage level Don't care Low-to-High Clock transition
1989 Sep 20
2
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
LOGIC DIAGRAM
MR 11 A0 B0 S0 5 4 3 D CP Q R SUM 2
F0
D
CARRY
CP CP 1 S R Q
R A1 B1 S1 6 7 8 D CP
SUM Q 9
F1
D
CARRY
CP
S R
Q
R A2 B2 S2 15 14 13 D CP
SUM Q 12
F2
D CARRY CP
S R
Q
R A3 16 B3 S3 17 18 D CP
SUM Q 19
F3
D
CARRY
CP
S R VCC = Pin 20 GND = Pin 10
Q
SF00931
1989 Sep 20
3
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Operating free-air temperature range Storage temperature PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -65 to +150 UNIT V V mA V mA C C
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free-air temperature range 0 PARMETER MIN 4.5 2.0 0.8 -18 -1 20 70 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, VOH High-level output voltage VIH = MIN, IOH = MAX Low-level output voltage Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX -60 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.5 2.7 3.4 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -20 -150 LIMITS TYP2 MAX V V V V V A A A mA UNIT
VOL VIK II IIH IIL IOS
ICC Supply current (total) VCC = MAX 55 80 mA Notes: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1989 Sep 20
4
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
AC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITION Waveform 1 Waveform 1 Waveform 2 Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN fMAX tPLH tPHL tPLH Maximum clock frequency Propagation delay, Cn to Fn Propagation delay, MR to Fn 105 3.0 3.5 4.0 TYP 140 5.0 5.5 6.5 8.0 9.0 9.5 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 90 2.5 3.5 4.0 9.0 10.0 10.5 MAX MHz ns ns UNIT
AC SETUP REQUIREMENTS
LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF, RL = 500 MIN ts (H) ts (L) th (H) th (L) ts (H) ts (L) tw (L) tREC (L) Setup time, High or Low An, Bn or Sn to CP Hold time, High or Low An, Bn or Sn to CP CP Pulse width High or Low MR Pulse width Low Recovery time MR to CP Waveform 3 Waveform 3 Waveform 2 Waveform 2 Waveform 2 12.0 12.0 0 0 6.0 6.0 6.0 8.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 12.0 12.0 0 0 6.0 6.0 6.0 9.5 MAX ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performances.
1/fmax CP VM tw(H) tPHL VM tw(L) tPLH VM Fn CP VM VM tW
MR
VM
VM
(L)
tREC
VM
Fn
tPHL VM
SF00932
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
SF00933
Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time
An, Bn, Sn
VM ts(H)
VM th(H)
VM ts(L)
VM th(L)
CP
VM
VM
SF00934
Waveform 3. Data and Select Setup and Hold Times
1989 Sep 20
5
Philips Semiconductors
Product specification
Quad serial adder/subtractor
74F385
TEST CIRCUIT AND WAVEFORM
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1989 Sep 20
6

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